Altium

Design Rule Verification Report

Date: 2016/11/2
Time: 14:55:04
Elapsed Time: 00:00:04
Filename: F:\PCB_Project\STEP V2.2\STEP V2.2.PcbDoc
Warnings: 0
Rule Violations: 3

Summary

Warnings Count
Total 0

Rule Violations Count
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk primitive without silk layer 3
Silk to Silk (Clearance=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Hole To Hole Clearance (Gap=8mil) (All),(All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Width Constraint (Min=3mil) (Max=100mil) (Preferred=5mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=3mil) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 3

Silk primitive without silk layer
Silk To Board Region Clearance (Out of silkscreen region) : Track (1169mil,1345mil)(1169mil,1705mil) Top Overlay
Silk To Board Region Clearance (Out of silkscreen region) : Track (1169mil,1705mil)(1369.37mil,1705mil) Top Overlay
Silk To Board Region Clearance (Out of silkscreen region) : Track (1169mil,1345mil)(1369.37mil,1345mil) Top Overlay
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